Parameter-Efficient Adaptation of High-Throughput Payment Routing Engines: Maintaining Transaction Velocity and Classification Invariance Under Lattice-Based Handshakes

• Christian P. Ramos

  College of Computer Science, Don Mariano Marcos Memorial State University, South La Union Campus, Agoo 2504, La Union, Philippines

  Author

• Mark Anthony S. Bautista

  College of Computing Studies, Information and Communication Technology, Isabela State University, Echague 3309, Isabela, Philippines

  Author

• Reynaldo M. Dela Cruz

  Department of Information Technology, College of Computing, Pangasinan State University, Urdaneta City 2428, Pangasinan, Philippines

  Author

Modern interbank payment clearinghouses process tens of thousands of real-time transactions per second across distributed settlement switches. The impending migration to post-quantum cryptography under NIST FIPS 203 (ML-KEM) and FIPS 204 (ML-DSA) standards introduces profound operational friction to high-velocity payment rails. Unlike compact classical elliptic curve keys, lattice-based public keys and digital signatures exceed standard Transmission Control Protocol (TCP) Initial Congestion Windows (IW10), forcing multi-segment packet fragmentation, connection establishment delays, and severe transport jitter during transport-layer security handshakes. When high-throughput routing switches ingest these fragmented, jittered transaction streams, downstream deep learning routing engines suffer acute representation drift, leading to misrouted payment corridors, queue congestion, and degraded clearing velocity. Full-parameter retraining of enterprise routing transformers is computationally prohibitive and risks catastrophic forgetting of historical liquidity and counterparty topologies. In this work, we propose a parameter-efficient adaptation framework specifically engineered for real-time payment routing engines operating over post-quantum transport rails. We formulate a mechanistic latency model demonstrating how lattice-based cryptographic handshakes induce tail latency inflation and representation displacement in neural routing classifiers. To preserve routing fidelity without heavy re-engineering, we adapt the parameter-efficient Low-Rank Adaptation (LoRA) architecture through a dualobjective loss formulation that simultaneously optimizes payment corridor dispatch accuracy and penalizes latent embedding drift under packet fragmentation jitter. Across an enterprise testbed processing 20,000 transactions per second modeled on ISO 20022 interbank messaging standards, our framework reduces trainable parameters by 99.4% compared to full fine-tuning while restoring routing classification invariance to 99.1% of unperturbed classical baselines. The adapted routing switch maintains sub-millisecond dispatch latency and prevents queue exhaustion during peak retail volume bursts, establishing an operationally viable pathway for post-quantum financial infrastructure modernization.

• PDF